Help on PCB stack up for FPGA with uC design

[marce]

As a rule of thumb for clocks I use 3x the standard route to route spacing for these nets, this reduces the chance of crosstalk and allows a GND guard track to be retro fitted if required.

 

[Sink0]

Thank you, just for information, when using swicthed power supply to generate FPGA 3.3V do you usually add a ferrit bead at the output for filtering purposes?