Mercury
Member level 3
simple spi
Hi!
I'm writing a simple SPI master interface in VHDL for a Coolrunner II CPLD. The clock rate is no higher than 20MHz. The data on MOSI line needs to appear a few ns before the rising edge of the clock, in order for the slave to catch the data.. But since the SCK line and the clock feeding the shift register are the same, the data will appear simultaniously with the clock (or even worse, the data will be delayed ). So the clock needs to be delayed with regard to data, but how is this achieved?
Best regards
George
Hi!
I'm writing a simple SPI master interface in VHDL for a Coolrunner II CPLD. The clock rate is no higher than 20MHz. The data on MOSI line needs to appear a few ns before the rising edge of the clock, in order for the slave to catch the data.. But since the SCK line and the clock feeding the shift register are the same, the data will appear simultaniously with the clock (or even worse, the data will be delayed ). So the clock needs to be delayed with regard to data, but how is this achieved?
Best regards
George