Help me to write the following program with VHDL

[bme.gol]

Help me to write the following program with VHDL
Frequency divider with a ratio of 34/53

 

[aquakeerthi]

let me show some sample example you just modify this and go ahead
The trend here seems to be to place the intended clock input divided by two into the integer range of variable cnt and the if statement checking the value of cnt. This should work for any input clock value, assuming you change the appropriate values
25.175MHz to 1Hz Clock Divider
entity c1hz is
port( clk:in bit; clkoutut bit);
end c1hz;

architecture behavior of c1hz is
begin
process(clk)
variable cnt : integer range 0 to 12587500;
begin
if(clk'event and clk='1') then
if(cnt=12587500)then
cnt:=0;
clkout<='1';
else
cnt := cnt+1;
clkout<='0';
end if;
end if;
end process;
end behavior;

 

[permute]

well, he probably wants a PLL. 34/53 is a rate that is between 3/4 and 1/2 of the clock rate. in your example, you can get 1/1, 1/2, 1/3, etc...

the alternative to a PLL/DCM based synthesizer would be to do:

if (x > y) then
  clk_out <= '1';
  x <= x - y + z;
else
  clk_out <='0';
  x <= x + z;
end if;

where z = 34, y = 53. this obviously has high jitter, as it basically looks like 010101010010101010101001 -- a clock but with occasional extra 0's.