danielhzhao
Junior Member level 1
ring vco
Designed a ring VCO using 0.18um CMOS process. The simulation tool is Hsp!ce. When measuring many different cycles (using .me@suRe statement), it was found that the durations per cycle were always changing. The design target is 1.140ns per cycle (about 877MHz), but the output varys from 1.138ns to 1.148ns. Anybody here can help me to reduce this variation of the VCO output?
Designed a ring VCO using 0.18um CMOS process. The simulation tool is Hsp!ce. When measuring many different cycles (using .me@suRe statement), it was found that the durations per cycle were always changing. The design target is 1.140ns per cycle (about 877MHz), but the output varys from 1.138ns to 1.148ns. Anybody here can help me to reduce this variation of the VCO output?