ameed
Advanced Member level 4
hi
i have already this thesis.
can anyone give me .vhd file in below thesis
K. Sinha, S. Roy and S. Sur-Kolay, "Design of a Redundant Radix 4 Arithmetic
Coprocessor using Field-Programmable Gate Arrays", B. Tech. Thesis, Kalyani
Government Engineering College, University of Kalyani, May 2001.
M. De and B. P. Sinha, “Fast Parallel multiplication using redundant quarternary
number system”, Parallel Processing Letters, Vol. 7, pp. 13-23 1997.
i have already this thesis.
can anyone give me .vhd file in below thesis
K. Sinha, S. Roy and S. Sur-Kolay, "Design of a Redundant Radix 4 Arithmetic
Coprocessor using Field-Programmable Gate Arrays", B. Tech. Thesis, Kalyani
Government Engineering College, University of Kalyani, May 2001.
M. De and B. P. Sinha, “Fast Parallel multiplication using redundant quarternary
number system”, Parallel Processing Letters, Vol. 7, pp. 13-23 1997.