Help me do two FSM design tasks

[seemagoyal44]

1.Design FSM that accepts all strings over 0 and 1 such that last bit have at least two 1's .Not to use more than 4 states.


2.design fsm that does 2/3 of input fruency .if input is 100 mhz and o/p should be 66mhz.

 

[vlsi_whiz]

Re: FSM questions

For the 2nd Q...u have to design a divide-by-1.5 ckt with 50% duty cycle..

When u divide 100 by 1.5 we get 66.666Mhz...

 

[seemagoyal44]

Re: FSM questions

i wann this answer using fsm.can u help out in detail

 

[vlsi_whiz]

Re: FSM questions

Well, to design this ckt. you may need to come up with two state machines.. one that operates on the +ve edge of clock and the other on the -ve edge of clock. You may have to or the output of these two FSMs to get the divide-by-1.5 ckt.

Will get u more details later...

Added after 7 minutes:

Ok, there's a simpler method using only one FSM.. First you design a divide-by-3 ckt using state machines...then from the output of the flip-flops of the divide-by-3 ckt, u pass these signals to a combinational logic ckt that generates this divide-by-1.5 clock.

U can refer to this document for this design. You have to write the code by urself.
Download it from here: