Help me design a LVDS receiver

[xstal]

Hi Friends,
so much has already been said and discussed about LVDS in this board, I still need your help as I am deeling with LVDS first time and need your help.

I have an LVDS out put with one pair of data lines and one pair of clock lines. I have to implement an LVDS receiver in an Spartan3E device. Please let me know how to design an LVDS Rx.

I have no idea of what is the output format and timing of the LVDS Tx that I am going to receive. Well, I can ask for this information from the vendor if I need it.
:?:What else do I need to know about the Tx part for which I will require for designing an LVDS Rx?

The LVDS Tx block power supply is 3.3V. :?:Can I use the IOs from a 2.5V bank to receive the signals. Because the max and min voltage levels of an LVDS signal will be different from 3.3V. :?:Can I use other remaining IOs for normal LVTTL application?

Thanks

 

[echo47]

LVDS Receiver.

LVDS specifies only the electrical characteristics. It doesn't specify any particular data format or data rate. You need to study your other device to determine what sort of communication logic you need in your FPGA.

General LVDS info in National's "LVDS Owners Manual":
**broken link removed**

If you apply the manufacturer-specified VCC to your LVDS driver, then it will output standard LVDS voltage levels, and your FPGA LVDS receiver will accept it fine. It doesn't matter if the driver and receiver VCC's are different, so long as they comply with manufacturer specs.

You mentioned "2.5V bank" and "LVTTL" in the same sentence, however Spartan-3E LVTTL requires 3.3V VCCO. Maybe you meant 2.5V LVCMOS instead of LVTTL?

For details on mixing LVDS and other I/O in one bank, see Tables 6 and 7 in Xilinx DS312, "Spartan-3E FPGA Family Complete Data Sheet".
**broken link removed**

 

[bharatsmile2007]

Re: LVDS Receiver.

Hi,

Can u expalin me "commom mode voltage" at the reciever in LVDS?

Thanks

 

[echo47]

LVDS Receiver.

Common mode voltage is the voltage between the differential pair and ground.

 

[karikalan_t79]

Re: LVDS Receiver.

lvds reference design in teh xilinx web for video application

 

[eziggurat]

Re: LVDS Receiver.

There is sample LVDS code in Lattice website https://www.latticesemi.com/products/developmenthardware/fpgafspcboards/71lvdsvideodemokit.cfm.