Help me design a counter with my conditions

[test_out]

Hi,

I want to design a counter with these conditions:

- When en = 1 counter start to count.
- After the counter count up to 36, stop.
- And then when en = 1 again, it begin to count.

But I couldnt make it start and stop as my desire.

Does any one has prete ideal for this?

 

[master.ro]

Re: Counter design!

try this. I think that will work but i don't have enough time to test it

process(en, cnt)
begin
if en='1' then
count <='1';
else if cnt = "100100" then
count <='0';
end if;
end if;
end process;

process(clk)
begin
if clk'event and clk='1' then
if count='1' then
if cnt<="100100: then
cnt<="000000";
else
cnt<=cnt+'1';
end if;
end if;
end process;

 

[pra]

Counter design!

which type of enable signal is that
is it +ve edge enable signal
or is it level sensitive!!!!!!!!

 

[koppolu1981]

Re: Counter design!

Hi test_out,
The specification on enable is not clear.
If enable is one the count will start and what happens to the enable after that.
This is important because the enable signal is critical for the specification u asked for.

Suppose if we consider that the enable signal will be at "high" only for a while, i.e just like some trigger pulse, then the design will be some thing like this.

We can add some comb-logic to give clock to counter which also depends the value of count and the enable signal.
I think this would help out.
check out for the block diagram..

 

[test_out]

Counter design!

Thank you all for your help,
Hi koppolu1981, In my case enable is not high for only a while but for long time, so do you have any ideal for this?

 

[koppolu1981]

Re: Counter design!

Hi test_out,
Even it is for a long time u can make that work by taking some care in comb-logic.
Like if the enable becomes zero before count of 36 your counter will stop working for some-time,i.e until it becomes high.
If the enable is high until the count reach 36 then the clock will continuosly be applied counter and the counter works continuously as a mod-36 counter.

 

[arp]

Counter design!

U can use this logic-----
use a reset signal to reset the counter initially..
if(reset)
{ cnt_en=0; cnt=0;}
if (cnt==36)
{ cnt_en=0; cnt=0;}
if (cnt_en)
cnt=cnt+1;
if (cnt==0 and en=1)
cnt_en=1;

this can be easily implemented in digital logic

 

[test_out]

Counter design!

Yeah, but can you give me some detail about comb_logic?

 

[koppolu1981]

Re: Counter design!

Yeah, but can you give me some detail about comb_logic?

Roughly the comb_logic can be written in this way.Pls check-out for VHDL/Verilog syntax for the below code.


inputs: clk,en,count[5:0]
output:clk_out

process
begin
if(count=36)
{ if(en=1)
clk_out<=clk;
else
clk_out<= 0;
endif;
}

elsif (count<36)

clk_out<= clk;

else

clk_out<= 0;

endif;
end process;


The above can still be optimised by writing some logic for count < 36 instead of comparing... even this will work.