Help me debug a Verilog code for a .dat. file

[UFK]

Verilog-debugging

Hiii

Iv been trying to run this particular piece of code for a .dat file. can someone please help me debug? it keeps giving me the following error

Module <test> has no port.


I made a .dat file as follows:

@002

11111111 01010101
00000000 10101010

@006

1111zzzz 00001111


Please help me with it.

 

[fcfusion]

Re: Verilog-debugging

Please explain what you're are trying to do. Your description says nothing. And add the code, without it we can't debug it.

 

[UFK]

Re: Verilog-debugging

hiii
im so sorry, im so stressed out i forgot to add the code.
Its as follows:

module test;
reg [7:0] memory [7:0];
integer i;

initial
begin

$readmemb("init.dat",memory);
for (i=0; i<8; i=i+1)
$display("memory [%0d]=%b",i,memory);
end
endmodule

The init.dat file is as under;

@002

11111111 01010101
00000000 10101010

@006

1111zzzz 00001111

Description:

What im trying to do is read an image on Verilog. I got a suggestion of using imread from MATLAB to convert an image to a matrix and then use it on Verilog but im unsure of how to do that.

can someone please help me...Thanks in advance

 

[fcfusion]

Re: Verilog-debugging

Here is the problem:

module test;

You should have at least one port, for example, a clock port.

Place one port even if you don't need it:

module test (input clk);

That should solve the problem

 

[UFK]

Re: Verilog-debugging

Thanks alot. That did solve my problem. It started giving me other errors about my init.dat file though (

 

[fcfusion]

Re: Verilog-debugging

Please be more specific about those errors. Perhaps we can do something about those too.

Word of warning: I doubt you can store Z values into registers !

 

[UFK]

Re: Verilog-debugging

Thankyou for your help. Ill be a little more specific about what im trying to do here. My project is about applying the SPIHT algorithm on fpga. Im trying to read an image file on Verilog. I got suggestions of converting an image into matrix using imread command from Matlab and then storing the matrix values as a txt file in Verilog using addresses such as @002 etc for a certain string of coefficients.

My init.dat file was an example code i was trying for a future larger matrix. Now that its giving me wierd errors im back on square one. Any suggestions?

Added after 2 minutes:

Here are the two errors that i got

line 28: Value 186286124 found at line 1 is not binary in call of system task $readmemb.
ERROR:Xst:2634 - "test.v" line 29: For loop stop condition should depend on loop variable or be static.

 

[fcfusion]

Re: Verilog-debugging

what kind of errors? compilation errors?

 

[UFK]

Re: Verilog-debugging

These are the two errors that i got

line 28: Value 186286124 found at line 1 is not binary in call of system task $readmemb.
ERROR:Xst:2634 - "test.v" line 29: For loop stop condition should depend on loop variable or be static.

 

[fcfusion]

Re: Verilog-debugging

First error: is there anything in your .dat file that isn't 0's or 1's?

Second error: You should use "begin" and "end" instructions to close the "for" loop

for (i=0; i<8; i=i+1)
begin
$display("memory [%0d]=%b",i,memory);
end

Besides that, memory[] is a register, not a variable. Registers require a clock signal and cannot be used like that inside an Initial statement. You should store your result in an Integer or Real.

You should declare memory[] as:

integer memory[7:0] (unsigned)
or
integer signed memory[7:0] (for signed numbers)

However integers are not synthesizable in this case, and serve for simulation purposes only. If you want the code to be synthesizable it will require more changes.[/quote]