HELP:Importing an IP Core in my Design and Simulating it.

[ryan023]

Hi!

I generated an Floating Point adder/subtracter using Core Generator and imprted the vhdl file in my project. The vhdl file imported was succesfully synthesised by it wasnt implementable. Why is this? and to simulate this in ModelSIM i have to import some new libraries? Help

THANKS!

Xilinix ISE - 12.3
ModelSim Altera 6.5b

Ryan Grixti

 

[FvM]

succesfully synthesised by it wasnt implementable

I don't get the meaning of the words. How can it be successfully synthesized without implementing the core?

 

[ryan023]

When I imported the VHDL file to my new project i tried to synthesis it with xilinix 12.3 and it did with a few warnings. Then i tried to implement the design and it stopped in the mapping. With the following errors:


ERROR:Map:116 - The design is empty. No processing will be done.
ERROR:Map:52 - Problem encountered processing RPMs.

Please do view the attached image.

Thanks for helping FvM.

 

[eshbonzie]

I believe the VHDL file shown in your attachment is nothing but a wrapper holding the values to create your core it has no logic inside(no one or more processes are running). Please attach the VHDL file itself of the core.

I would suggest to write another VHDL file in which you use your core as an a component to which you pass some values and do whatever the core does on these values and then read them back again...I believe this way it would be implemented.

Eshbon!

 

[FvM]

I don't see a problem in using a component, e.g. an IP core as top entity in a design and synthesize it. I often did this for test purposes. But I'm not familiar with the Xilinx tool chain and don't know about the popular mistakes when using it. As a general requirement common to all tools, the exact entity name exposed by the IP core must be known to the compiler.

 

[ravics]

I think you have NOT added the IP core component and port mapped into your design. You need to do that by viewing HDL Instantiation Template under Implementation.

For simulation using ModelSim you need to Compile HDL Simulation Libraries (Design Utilities) under Behavioral Simulation and in "properties" of "Compile HDL Simulation Libraries" you need to add the path where your Xilinx ISE is located.