TERRYWU3
Member level 1
ep2c8
Dear Sir,
I have something confused in FPGA design. Would you please give me any suggestion ?
My FPGA is CYCLONE II EP2C8-208
1. SDR SDRAM control :
May I always enable CKE and always disable DQM for saving my IOs ?
2. SPI serial flash :
- There is a "hold" pin , I need to read/write SPI flash , but this pin seems not
necessary . I want to pull high this pin , is it correct ?
- How many ways to burn data into SPI flash if my data quantity above 16 Mbit ?
My data is picture (BMP format ) , I think that burn speed is important , so
RS-232 transmission is not suitable.
3. If it possible to place an JPEG decoder into EP2C8 ?
How many logic cell does it need ?
4. I add a MCU ( like 8051 ) to communicate with FPGA . If it usable that only use:
data [7..0] => play a address and data bus
clk => strobe signal
RS => for FPGA to recognize data[7..0] is data or address
5. About FPGA Vccint 1.2V , I dont know FPGA power consumption because design
is not finished yet , but my hardware must ready before ,I want to use AME1117
to adjust 1.2V for Vccint , is it OK ?
6. PLL : Does EP2C8 internal PLL could random modified ?
Now I place a clock generator ( ICS307 )
Would you please give me any suggestion for these questions ?
Very very thanks ~
Dear Sir,
I have something confused in FPGA design. Would you please give me any suggestion ?
My FPGA is CYCLONE II EP2C8-208
1. SDR SDRAM control :
May I always enable CKE and always disable DQM for saving my IOs ?
2. SPI serial flash :
- There is a "hold" pin , I need to read/write SPI flash , but this pin seems not
necessary . I want to pull high this pin , is it correct ?
- How many ways to burn data into SPI flash if my data quantity above 16 Mbit ?
My data is picture (BMP format ) , I think that burn speed is important , so
RS-232 transmission is not suitable.
3. If it possible to place an JPEG decoder into EP2C8 ?
How many logic cell does it need ?
4. I add a MCU ( like 8051 ) to communicate with FPGA . If it usable that only use:
data [7..0] => play a address and data bus
clk => strobe signal
RS => for FPGA to recognize data[7..0] is data or address
5. About FPGA Vccint 1.2V , I dont know FPGA power consumption because design
is not finished yet , but my hardware must ready before ,I want to use AME1117
to adjust 1.2V for Vccint , is it OK ?
6. PLL : Does EP2C8 internal PLL could random modified ?
Now I place a clock generator ( ICS307 )
Would you please give me any suggestion for these questions ?
Very very thanks ~