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luancao said:To make it simple, let's descibe in the following way.
First, you will have a clear specification in your DDR controller interface. The timing diagram specified the frequency, duty cycle, setup, hold time etc, in most cases, with max and min in a range.
Then, you convert this timing specification to the controller equivallent time. That is, you specify the timing requirement in your design that satisfies the timing diagram your specification. After you get it done, you will have to check the timing in SPEC one by one to see if each of them are satisfied and there is no confliction in them.
Finally, you write the above timing reqirement in the script of the STA tools and debug it to make it work in your STA enviroment.
You could find some example. But I think it may spend more time than just get it from the SPEC timing diagram.
luancao said:To make it simple, let's descibe in the following way.
First, you will have a clear specification in your DDR controller interface. The timing diagram specified the frequency, duty cycle, setup, hold time etc, in most cases, with max and min in a range.
Then, you convert this timing specification to the controller equivallent time. That is, you specify the timing requirement in your design that satisfies the timing diagram your specification. After you get it done, you will have to check the timing in SPEC one by one to see if each of them are satisfied and there is no confliction in them.
Finally, you write the above timing reqirement in the script of the STA tools and debug it to make it work in your STA enviroment.
You could find some example. But I think it may spend more time than just get it from the SPEC timing diagram.