DDR4 SDRAM

[Musawir]

I am going to design DDR4 SDRAM in verilog.
So the below figure shows the memory subsystem as DDR controller, DDR PHY and DDR DRAM.

I have to design all of these subsystem? From where I will start?
Please alse refer me some good materials related to DDR4 SDRAM. Thanks

 

[dpaul]

@Musawir
To me it is still not clear whether you want to design the memory itself or only the memory controller core!

If it is the controller core, someone named @promach tried to do something in this direction. You should search out his posts.

https://www.edaboard.com/threads/ddr3-memory-implementation.395967/

I also found something at GitHub : https://github.com/buttercutter/DDR

 

[Musawir]

@Musawir
To me it is still not clear whether you want to design the memory itself or only the memory controller core!

If it is the controller core, someone named @promach tried to do something in this direction. You should search out his posts.

https://www.edaboard.com/threads/ddr3-memory-implementation.395967/

I also found something at GitHub : https://github.com/buttercutter/DDR

Thanks for your kind response.
As I am new to DDR. Now I am just following the DDR4 standard JEDEC spec. I want to implement the whole system as in the above figure. Is it possible first design a memory module and then the memory controller?

 

[Musawir]

Do we need DDR PHY Interface between Memory Controller and DDR DRAM Memory?

 

[dpaul]

Is it possible first design a memory module and then the memory controller?

A simulation model of the memory in Verilog is always provided by the manufacturer. No need to write that on your own. You can focus on the memory controller part.

 

[Musawir]

Do we need DDR PHY Interface between Memory Controller and DDR DRAM Memory?

@dpaul
Please comment on this.

 

[FvM]

Do we need DDR PHY Interface between Memory Controller and DDR DRAM Memory?

Generally, yes.
You say you are using JEDEC DDR4 spec as a guide, so you should already have a brief idea which specific functions need to be implemented between logical interface layer implemented in memory controller and I/O buffers.