Hdl coding from the synthesis point of view

[rsjgs]

synthesis help

can anyone give me an alternative for the use of loops? Also any guidance on hdl coding from the synthesis point of view?

 

[hawkbw]

synthesis help

maybe the reference of synthesising tooles will you
hint
for example Xilinx ISE's reference ,you can get it at the Help , or company's web..........

 

[sree205]

synthesis help

module (clk,count,datain,dataout);

input clk,datain;

reg [3:0] count,internal_reg;

always@(posedge clk)
count <= count + 1'b1;

always@(posedge clk)
if(count <= 4'b1111)
internal_reg[count] <= datain;

endmodule

this is one way of using the loops. I'm sure this is synthesizable.