Generating wide range LO frequency synthesizer problems

[AhlaPlaster]

Hello,
I am trying to develop a synthesizer that will supply changeable LO signal between 950MHz to 2300MHz or at least between 950MHz to 2070MHz. I need this synthesizer to achieve frequency lock as fast as possible, let's say 500uS maximum.
From what I found in order to achieve this wide range of frequency I'll have to use a synthesizer which generates a higher frequency and then output divider. If I understand right (this is my first project) this production of LO frequency will create many unwanted spur signals.

Currently I have ADF4350 synthesizer: Datasheet
It is possible for me to buy another PLL and VCO or a full synthesizer that will help me to achieve better performances.
My channel spacing/pfd seems to be 8MHz, I think that I may make it greater if it will be needed.
And my reference clock will probably be a multiply of 8MHz sine-wave with about 3dBm signal power.

If it is possible I would like you to consult me how can I suppress this spur signals and maybe tell me more about the problems that may appear because of them.

Sorry about my English and thank you very much,
Erez.

 

[barry]

The ADF4351 has better performance. What exactly are you looking for? You may have lots of spurs of low amplitude, or fewer spurs of higher amplitude.

 

[AhlaPlaster]

This LO generator should be connected to a mixer that will downconvert the RF input. After the downconversion there will be an IF filter so that I will be able to sample it with ADC and have a resolution of about 67kHz. I don't know exactly which spurs appearnce is better in this application but I need to receive the best quality signal I can get at the IF port of the mixer. Most of all I afraid of in band interferences.
I have also found a synthesizer of Linear that seems to have much better spur suppression but I think that it doesn't ment to be used as fast locking synthesizer, this -do you think that it may be better for my project?

 

[barry]

That LT part requires you to program your divider using the SPI interface. Is that fast enough to meet your 500 uS requirement? That's in addition to the lock-time of the PLL, which depends on your filter, frequency step size, etc.

 

[AhlaPlaster]

All of the plls/synthesizers are using serial interface. My project will probably work at 136MHz clock so it won't hurt the lock time too much. The problem is the loop filter. As much as I know in order to get better phase noise performances I need to use smaller bandwidth loop filter - the tradeoff is the damage to the locking time, at the ADF4350 and 4351 we can use the fastlock switch that changes the cutoff frequency of the filter and gets it closer to the locking stage pretty fast. Unfortunatly the LT6946 don't have this kind of switch.

 

[biff44]

yes, ANY PLL on a chip will use a divider to make the lower frequencies. That means u need to switch in lowpass filters for different output bands of frequencies (or just live with the 3rd, 5th harmonics).

Hittite makes a similar PLL chip with good performance too.

500 uS IS POSSIBLE, but tight. You will find a significant portion of the tuning time taken up by the spi bus communicating the register values to the PLL. That ADF4350 needs some registers sent twice and in the right order, gawd knows why. You will want a very fast bus clock, and not too much distance from the controller to the PLL chip.

Alternatively, you could use two independent PLLs and a SPDT switch

 

[AhlaPlaster]

Well the SPI really doesn't that affective. Even if it is I really want to focus on eliminating the spur signals at this range of frequencies.
I know that the ADF 4350 has fastlock switch but I'm not so sure about its spur performances, on the other hand the LT part should have great spur suppression but its lock time seems to be a problem in my design.
Using two different synthesizers will cause more noise in the processing card unless I can find two chips with muting function. Thats way I may get two frequencies to lock at the same time without interfering one another.

 

[vfone]

ADF4350 has a register (DB5) which enable or disable the RF output.

 

[AhlaPlaster]

Yes I figured it after writing the last post, it seems to be usefull if I will decide to use it at this operation. I am also trying to find two different synthesizer that will be able to do the same and be specified to work at narrower range of frequencies so they won't use VCO output divider and then have lower and more predictable harmonics. That way it will be easier to filter the output frequency. I also realised that the ADF4350 has a great dithering function for the PFD spurs by taking a little bit damage to the phase noise.

 

[BigBoss]

For better signal purity, you should use a N-Integer PLL and seperate high perfomance VCO ( www.synergymicrowave.com).
Fractional synthesizers are more noisy from spurs point of view compare to integers(because of taking mean value of divided signal).Also, integrated VCO+PLL is worse than VCO and PLL in terms of spurs and phase noise.

 

[AhlaPlaster]

But if I am using PLL with seperate VCO I can't use muting (which enables locking at the same time) so I'll need to use only one synthesizer circuit or I'll have alot noise at this area. Also one VCO that generates fundemental frequencies according to my needs is unavailable, or that it will be needed a tuning voltage between 0.5V to 25V so that the loopfilter will be very complexed one and noisy also. I will have to get a high frequencies VCO and use an output divider which is another component, from what I found this components aren't that good so in the end I think that the circuit will be much more complexed and won't improve the noise/spur performances that much.
The ADF4350 can be used as an integer N PLL.