aaruljain
Newbie level 2
Hi,
I have a divide-by-2 clock in the design which is then muxed with TEST_CLK and also another functional clock before being used in the design.
Now my question is what is the difference between creating a generated clock at the output of divider and creating a generated clock at the output of mux?
Regards
I have a divide-by-2 clock in the design which is then muxed with TEST_CLK and also another functional clock before being used in the design.
Now my question is what is the difference between creating a generated clock at the output of divider and creating a generated clock at the output of mux?
Regards