gate level simulation going wrong for counter DUT

[vlsi_maniac]

i am new to gate level simulation.
i am using altera quartus and modelsim.
i have done place & route,generated sdo & vo files.
my DUT is a simple counter and works at 260MHz targeted at stratix.
now how should i decide how much time i should apply reset to the DUT (i have applies for a period of 4 clocks)
and if i apply clock for a period of 10ns(100 MHz) i am getting some values in counter but there are transitions during some clocks-not at edges but in between clocks.
if i apply clock for a period of 4ns(250MHz)the DUT is not working.
below is the DUT code

module counter_test(
core_clk,
reset_n,
count );

input core_clk;
input reset_n;
output [7:0]count;

wire core_clk;
wire reset_n;

reg [7:0] count;

always @ (posedge core_clk or negedge reset_n)
if(~ reset_n)
count <= 8'd0;
else
count <= count + 8'd1;
endmodule

testbench :

`timescale 1 ps/ 1 ps

module tb_counter ();

reg core_clk;
reg reset_n;
wire [7:0] count;

initial
begin
core_clk <= 1'b1;
forever #2000 core_clk <= ~ core_clk;
end

initial
begin
reset_n <= 1'b0;
repeat(4) @(posedge core_clk);
reset_n <= 1'b1;
end

counter_test counter_u1(
core_clk,
reset_n,
count);

endmodule

thanks

 

[Syswip]

transitions during some clocks-not at edges but in between clocks

Because you have timing delays. Try to reduce your clock up to 1 MHz and see what happens.

Good luck!