Full custom design & transistor modeling

[Wawan66]

Hi everyone,

I have just few questions. In fact, I'm working with cadence virtuoso in order to create a schematic of an inverter. I use a design kit in 90nm technology. Obviously, I can alter some parameters of transistor as width or length. But, I don't know the meaning of 2 of them : "mismatch" and "fingers". Can you help me? I'd very thankful.

 

[nitu]

Hi..
The mismatch parameter is used to allow models to simulate mismatch simulation. As you might be knowing that two transistor no matter how close they are, can have mismatch between them. Mismatch parameter is set to 1 in order to allow simulator to run mismatch simulation on these devices to analyse mismatch impact on circuit performance.

To explain finger let us consider a case. Let us have one transistor with transistor width 10u and let us have two transistor with width 5u each. If I connect these 5u transistor in parallel then total current following through them would be same as that of 10u. We might say that we have 2 fingers of 5u each for realization of 10u transistor. So, finger parameters specifies in how many equal sized finger the transistor would be implemented or drawn in layout.

I hope this helps..

 

[erich123]

Hi..
The mismatch parameter is used to allow models to simulate mismatch simulation. As you might be knowing that two transistor no matter how close they are, can have mismatch between them. Mismatch parameter is set to 1 in order to allow simulator to run mismatch simulation on these devices to analyse mismatch impact on circuit performance.

Hi Nitu,

What does "mismatch" mean exactly? ---Parameter variation due to location difference? Could you explain that more clearly?

 

[nitu]

Hi..
Mismatch here is referred as device variation. Some SPICE models have mismatch values for local device variation. They need certain parameter to be set to be able to find on which devices we want mismacth simulation to be run.
This mismatch can be in terms of Threshold voltage and Mobility or may in terms of width and length. SPICE model contains which type of mismatch distribution like gaussian or uniform is valid for these devices along with values of standard deviation, mean for these distribution. Simulation tools takes all these information and runs mismatch or to say monte carlo simulation on the devices on which this mismatch flag is set to one.

Please note that mismatch is not general parameter i.e. some SPICE models can still allow the mismatch simulation even with mismatch flag set to 0. Here I only mentioned the intent behind have mismatch flag.

 

[Wawan66]

Ok, thanks alot for your helps. It's more clear now to me. Maybe, I'll have another questions. My goal is to generate automatically some netlist in order to simulate components with Cadence Spectre tool. So I need to know the different parameters I can change.

 

[Wawan66]

Some more questions! It's just all about layout. Can someone explain the meaning of these elements please : a strap (for example NWELL/PWELL strap) ? A well tie ? Thanks alot for your help.

 

[aaronkong]

stap is the sub

 

[onlymusic16]

well tie is used to avoid latch up problem.

If i am gettig you right, you want to generate the netlist automatically through virtuoso. You will need to setup your ADE environment before you can generate the netlist.