f.ullah99
Newbie level 1
Hi
I am designing Divider block for the PLL. Can someone give the guideline that how in cadence the frequency is applied to the (CK and -ive CK) input of the divider. Thanks
I am designing Divider block for the PLL. Can someone give the guideline that how in cadence the frequency is applied to the (CK and -ive CK) input of the divider. Thanks