Free VHDL simulator for wave form viewing

[garvind25]

Hi,

Does anyone know of any free IDE where one can write, compile, simulate VHDL codes and view associated waveforms? I tried Sonata by Symphony but I could not find any option to force values to the input ports in the waveform viewer (in other words I will need to write a separate testbench to view the output).

I am looking for something like Xilinx ISE to create tutorials for beginners. If one needs to write a separate test bench to simulate and see the output, the beginners may have a problem. I am planning against using Xilinx ISE as it is complicated.

Any pointers towards any other free software/ how to force waveforms in Sonata waveform viewer will be thankfully acknowledged.

Thanking You,
Arvind Gupta

 

[dpaul]

Take a look at EDA Playground.

EDA Playground

Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.

www.edaplayground.com

 

[garvind25]

Take a look at EDA Playground.

EDA Playground

Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.

www.edaplayground.com

Thanks for your reply. It has two sub-windows,; one for the code and the other for teh test bench. Anyways, can it be used to simulate and see wwaveforms without having to write a test bench ?

 

[dpaul]

Anyways, can it be used to simulate and see wwaveforms without having to write a test bench ?

For the 1st time in my life I have someone wanting to simulate a design without creating a test-bench!
Who am I dealing with?

 

[ads-ee]

Anyways, can it be used to simulate and see wwaveforms without having to write a test bench ?

For the 1st time in my life I have someone wanting to simulate a design without creating a test-bench!
Who am I dealing with?

I've seen this methodology before...

Lots of Modelsim .do force files (without comments), not something I'd recommend doing.

 

[dpaul]

Lots of Modelsim .do force files (without comments), not something I'd recommend doing.

Me too. Forcing one or two signals for a quick and dirty debug is ok, but forcing signals and trying to verify a design can never ever be a way to simulate!

And I still do not understand this part from the OP:

I am looking for something like Xilinx ISE to create tutorials for beginners. If one needs to write a separate test bench to simulate and see the output, the beginners may have a problem. I am planning against using Xilinx ISE as it is complicated.

No, why? It means then those beginners do not have the proper education or guidance in testing a design. A proper methodology must be followed.

 

[ThisIsNotSam]

if you say ISE is too complicated, then your bar is really low. these are not beginners, these are completely untrained individuals.

 

[garvind25]

Hi,



Thanks for the responses.



Ok, let me clarify. Consider that I want to simulate a 2-input AND gate. Let the inputs be ‘A_in’ & ‘B_in’ and the output be ‘C_out’. Accordingly, I am looking for either of the following:



** As in Xilinx ISE (eg. ver. 10.1) where one can toggle the input waveforms A_in and B_in to generate all the four input cases (00, 01, 10, 11). Then run the simulation and view the waveforms for both the inputs and the expected output.

** As in Modelsim (eg. Student edition), where after opening the simulation window, one can right click on an input value (A_in and B_in in this case) and select the ‘Force’ option to enter the input string (For eg: A_in as ‘0011’ and B_in as ‘0101’). Then click the ‘Play button’ to watch the output waveform as per the input waveform cases.


The target audience are ppl. Who are studying / have just studied Digital electronics and want to try out VHDL design with small number of inputs. I simply don’t want to burden the newbies with writing a text case. That’s why this query.


Looking for your reply.

Regards,

Arvind Gupta.

 

[dpaul]

I would still insist on writing a testbench. Even for a 1 input NAND gate DUT.
Advantages:
1. It will save time forcing the signals manually and viewing the output manually
2. Since the TB will drive the inputs and can also be made to check the output (self-checking TB), it will help to reduce human perception errors.

Q: How long will the students manually verify a NAND gate or a half/full adder? I mean they are just two small lab exercises. Sooner or later they must learn to use a create an effective TB, so why not from the beginning?

You should show them the use of the "force" but do not give them an impression to use it as a means to verify extremely small designs.

 

[FlyingDutch]

I would still insist on writing a testbench. Even for a 1 input NAND gate DUT.
Advantages:
1. It will save time forcing the signals manually and viewing the output manually
2. Since the TB will drive the inputs and can also be made to check the output (self-checking TB), it will help to reduce human perception errors.

Q: How long will the students manually verify a NAND gate or a half/full adder? I mean they are just two small lab exercises. Sooner or later they must learn to use a create an effective TB, so why not from the beginning?

You should show them the use of the "force" but do not give them an impression to use it as a means to verify extremely small designs.

Hello,

here is best series of lectures related to Verilog (41 lectures) I has ever seen, from simple design like full-adder to project of RISC CPU. From beginning lots of attention is pay for simulation and writing test benches. It is worth to be viewed:

Best Regards