Sumathigokul
Member level 1
Is there any relationship among resource utilization and total power consumption of digital design??? If it is so, then can you justify the the following ??? (generated using Libero IDE)
Design 1:
Core Cells: 7 of 260 (3%)
IO Cells : 10
Total power consumption : 4.998 mW
Static power consumption : 1.56 mW
Dynamic power consumption : 3.438 mW
Design 2:
Core Cells: 20 of 260 (8%)
IO Cells : 11
Total power consumption : 4.369 mW
Static power consumption : 1.23 mW
Dynamic power consumption : 3.139 mW
How is it possible that higher circuit utilization reduces its total power consumption????
Design 1:
Core Cells: 7 of 260 (3%)
IO Cells : 10
Total power consumption : 4.998 mW
Static power consumption : 1.56 mW
Dynamic power consumption : 3.438 mW
Design 2:
Core Cells: 20 of 260 (8%)
IO Cells : 11
Total power consumption : 4.369 mW
Static power consumption : 1.23 mW
Dynamic power consumption : 3.139 mW
How is it possible that higher circuit utilization reduces its total power consumption????