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[SOLVED] FPGA Help!! (change value of variable)

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arkoulikosta

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Hi, i need help programming a flex10k
I am trying to change the display of a seven segment every time the clock rises.
here is my main code:

Code VHDL - [expand]
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
ENTITY roll IS
    PORT (Clock :IN STD_LOGIC;
            out7seg :OUT STD_LOGIC_VECTOR (6 DOWNTO 0));
END roll;
 
ARCHITECTURE Behavior OF roll IS
BEGIN
 
    PROCESS(Clock)
    BEGIN
        IF Clock'EVENT AND Clock='1' THEN
            out7seg<= 
            
                END IF;
    END PROCESS;
END Behavior;


My problem is that i have no idea how to put different outputs every time an event happens.
My theory so far is to have a matrix with the values that i want for the 7 segment and rotate them.
Why can this be done in VHDL?
I appreciate any help!
 
Last edited by a moderator:

try adding a counter, and using the counter value to do stuff
 

Code VHDL - [expand]
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use ieee.numeric_std.all;
 
....
 
signal counter : unsigned(7 downto 0) := x"00";
 
PROCESS(Clock)
BEGIN
  if rising_edge(clk) then
    counter <= counter + 1;
 
  END IF;
END PROCESS;
 
...etc
 

Thanks for your help, but still i cant figure it out...
Code: 
ARCHITECTURE Behavior OF roll IS
BEGIN

signal counter : integer := 0;

	PROCESS(Clock)
type array_type is array (0 to 3) of std_logic_vector(6 downto 0);
signal array_name : array_type;   

	BEGIN
array_name(0) <= "0001011";
array_name(1) <= "0001011";
array_name(2) <= "0001011";

		out7seg<="0000000";
		IF Clock'EVENT AND Clock='1' THEN
			if counter=1 then
			     out7seg<=array_name(0);
                        elsif counter=2 then
			     counter <= array_name(1);


                        ....... etc
			end if;
		END IF;
	END PROCESS;
END Behavior;


Can anyone help me correct this code? i am trying to use an array to save the values that i want
and depending on the counter the output will take different values, where are the mistakes??
 

what happened to incrementing the counter? the line: counter <= counter + 1; tricky posted.

also, in cases like this you may want to look at a case statement. will make the code a bit easier to read.

oh, you're assigning your output in two places. you don't need to assign your array to counter.
 

Code: 
ARCHITECTURE Behavior OF roll IS
BEGIN

signal counter : integer := 0;

PROCESS(Clock)

type array_type is array (0 to 3) of std_logic_vector(6 downto 0);
signal array_name : array_type;   

	BEGIN
array_name(0) <= "0001011";
array_name(1) <= "0001011";
array_name(2) <= "0001011";


		IF Clock'EVENT AND Clock='1' THEN
			if counter=1 then
			     out7seg<=array_name(0);
            elsif counter=2 then
			     counter <= array_name(1);		
			end if;
		counter<=counter+1;
		END IF;
	END PROCESS;
END Behavior;

yeah you are right i forgot to put the increment, but that is not my problem

Here are the problems that apear when i try to compile:
Χωρίς τίτλο.jpg

I have no idea how to correct them........ help!!!!!


line 17 --> signal array_name : array_type;

line 26 --> if counter=1 then

line 28 --> elsif counter=2 then

line 29 --> counter <= array_name(1);
 

your types and signal declarations should be between the architecture statement and begin

architecture behavior ...

signal xxxx...

begin

also, you don't want to assign array_name to coutner, you want to assign it to out7seg in your 2nd if

try initializing your array in the signal assignment step
 

first of all - follow gbounce's advice - signals can only be declared in architectures, not processes.
Secondly, array_name should be a constant, and it should not be an array. Just declare 4 different constants:

Code: 
if counter = 0 then
  out7Seg <= CONSTANT1;
elsif counter = 2 then
  out7seg <= CONSTANT2;
---etc
 

It seems you're really not getting it. Here try something like this. An alternative to the "for loop" would be a circular buffer (shift register) to shift out the array contents.

Code: 
library ieee;
use ieee.std_logic_1164.all;

entity sseg_seq is
	port (
		CLOCK_50	: in std_logic;
		KEY  : in std_logic_vector(0 downto 0);
															 -- KEY(0) = reset
		HEX0 : out std_logic_vector(6 downto 0);
		HEX1 : out std_logic_vector(6 downto 0);
		HEX2 : out std_logic_vector(6 downto 0);
		HEX3 : out std_logic_vector(6 downto 0);
		HEX4 : out std_logic_vector(6 downto 0);
		HEX5 : out std_logic_vector(6 downto 0);
		HEX6 : out std_logic_vector(6 downto 0);
		HEX7 : out std_logic_vector(6 downto 0)
	);
end sseg_seq;

architecture behav of sseg_seq is
	subtype reg is std_logic_vector(6 downto 0);
	type reg_array is array (0 to 7) of reg;
	signal HEX_array : reg_array;
	signal CLOCK_TICK : std_logic;
begin
	-- output logic
	HEX0 <= HEX_array(0);
   HEX1 <= HEX_array(1);
   HEX2 <= HEX_array(2);
   HEX3 <= HEX_array(3);
   HEX4 <= HEX_array(4);
   HEX5 <= HEX_array(5);
   HEX6 <= HEX_array(6);
   HEX7 <= HEX_array(7);
	
	process(CLOCK_TICK, KEY)
	begin
		if KEY(0) = '0' then
			HEX_array(7) <= "1111111";
			HEX_array(6) <= "1111111";
			HEX_array(5) <= "1111111";
			HEX_array(4) <= "0001011";
			HEX_array(3) <= "0000110";
			HEX_array(2) <= "1000111";
			HEX_array(1) <= "1000111";
			HEX_array(0) <= "1000000";
		elsif falling_edge(CLOCK_TICK)	then
			HEX_array(0) <= HEX_array(7);
			out_gen : for n in 1 to 7 loop
				HEX_array(n) <= HEX_array(n-1);
			end loop out_gen;
		end if;
	end process;
	
	process(CLOCK_50, KEY(0))
		variable cnt : integer := 0;
	begin
		if KEY(0) = '0' then
			cnt := 0;
		elsif (CLOCK_50'event and CLOCK_50 = '1') then
			if (cnt = 4999999) then
				CLOCK_TICK <= not CLOCK_TICK;
				cnt := 0;
			else
				cnt := cnt + 1;
			end if;
		end if;
	end process;
			

end behav;
 
Last edited:

The code you have posted is not great because you have created a logic clock divider - something that should be avoided at all costs.
 

TrickyDicky said:
The code you have posted is not great because you have created a logic clock divider - something that should be avoided at all costs.
Click to expand...

Correct it did, it was code I made while I was taking a class. It's probably better to use the 'tick' as a clock enable - or better yet a PLL or DCM with the divided frequency I'm assuming?
 

its best just to use a clock enable whereever possible - keep everything in the same clock domain.
And with such a slow clock, a DCM or PLL cannot be used (afaik, the slowest clock they can output is 1 or 2 MHz)
 
Thanks to all,

i created contants instead of an array and fixed the decleration part,
however i still get error in line "if count=1 then"
error: VHDL syntax error:found illegal character'

Code: 
ARCHITECTURE Behavior OF roll IS

Constant one: STD_LOGIC_VECTOR (6 DOWNTO 0):="0000001";
Constant two: STD_LOGIC_VECTOR (6 DOWNTO 0):="0000011";

BEGIN

PROCESS(Clock)

variable count : integer;

	BEGIN
		count<=0;

		IF Clock'EVENT AND Clock='1' THEN
			if count=1 then
			     out7seg<=one;
            elsif count=2 then
			     out7seg<= two;		
			end if;
		count<=count+1;
		END IF;
	END PROCESS;
END Behavior;

How can i fix that?
 

because you've made count a variable and not a signal, you have to assign it with :=

also, dont assign it to zero at the top of the process, or it will never increment.
 

TrickyDicky said:
because you've made count a variable and not a signal, you have to assign it with :=

also, dont assign it to zero at the top of the process, or it will never increment.
Click to expand...

I deleted the count<=0;
I changed the variable count := integer; but still the same error
Also tried changing if count=1 then but same problem
 

repost the code (all of it) - are you sure the error points to that line?
 

Thank you, i appreciate the help

Try 1:
Code: 
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY roll IS
	PORT (Clock :IN STD_LOGIC;
			out7seg:OUT STD_LOGIC_VECTOR (6 DOWNTO 0));
END roll;

ARCHITECTURE Behavior OF roll IS

Constant one: STD_LOGIC_VECTOR (6 DOWNTO 0):="0000001";
Constant two: STD_LOGIC_VECTOR (6 DOWNTO 0):="0000011";
variable count := integer;

BEGIN

PROCESS(Clock)


	BEGIN
		

		IF Clock'EVENT AND Clock='1' THEN
			if count=1 then
			     out7seg<=one;
            elsif count=2 then
			     out7seg<= two;		
			end if;
		count:=count+1;
		END IF;
	END PROCESS;
END Behavior;

Errors:
Χωρίς τίτλο1.jpg

Try 2:
Code: 
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY roll IS
	PORT (Clock :IN STD_LOGIC;
			out7seg:OUT STD_LOGIC_VECTOR (6 DOWNTO 0));
END roll;

ARCHITECTURE Behavior OF roll IS

Constant one: STD_LOGIC_VECTOR (6 DOWNTO 0):="0000001";
Constant two: STD_LOGIC_VECTOR (6 DOWNTO 0):="0000011";
variable count := integer;

BEGIN

PROCESS(Clock)


	BEGIN
		

		IF Clock'EVENT AND Clock='1' THEN
			if count:1 then
			     out7seg<=one;
            elsif count:2 then
			     out7seg<= two;		
			end if;
		count:=count+1;
		END IF;
	END PROCESS;
END Behavior;

errors:
Χωρίς τίτλο2.jpg


Line 13: variable count := integer;
Line 24:if count:1 then
line 26:elsif count:2 then
 

you cant decalre variables in an architecture, only signals.
you have to declare the variable inside the process.
 
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