ywguo
Junior Member level 2
Hi, Guys,
RTL vs. netlist verification failed using Formality. I checked the RTL code and synthesized netlist. Actually, the netlist was right. The fail is just because that some registers and gates are reduced that were always '0' or '1'.
How can I solve this problem?
Thanks
Yawei
RTL vs. netlist verification failed using Formality. I checked the RTL code and synthesized netlist. Actually, the netlist was right. The fail is just because that some registers and gates are reduced that were always '0' or '1'.
How can I solve this problem?
Thanks
Yawei