billyc59
Junior Member level 1
formality error: "use of undeclared identifier std_logic vector" FMR_VHDL-011
Hi,
I'm trying to load my Synopsys design compiler-generated netlists into formality and I am getting the above error.
use of undeclared identifier "std_logic vector" FMR_VHDL-011
I'm very confused by this issue as the netlists were generated by a tool and not hand-coded. This particular module is also the top-level design file for my entire project. the sub-modules have no trouble being loaded. This error is occuring when I try to load the implementation files, and not the RTL reference files. Does Formality recognize module dependancy?
please help.
Hi,
I'm trying to load my Synopsys design compiler-generated netlists into formality and I am getting the above error.
use of undeclared identifier "std_logic vector" FMR_VHDL-011
I'm very confused by this issue as the netlists were generated by a tool and not hand-coded. This particular module is also the top-level design file for my entire project. the sub-modules have no trouble being loaded. This error is occuring when I try to load the implementation files, and not the RTL reference files. Does Formality recognize module dependancy?
please help.