oAwad
Full Member level 2
Hello all,
I want to know if it's normal for std cell libraries to have their std cells with non-tied bulk transistors. I'm using Nangate 45nm library and found that transistors in std cells GDS have floating bulks while their schematics have bulks correctly connected. So how Nangate give out a cell library with cells that is not correctly connected ? (I knew this from performing LVS check on one std cell from this library)
Am I supposed to specify anything in "Place" tab in SoC Encounter (maybe Physical Cells or Tie HI/LO) to tie the transistor bulks ?
Any thoughts ?
I want to know if it's normal for std cell libraries to have their std cells with non-tied bulk transistors. I'm using Nangate 45nm library and found that transistors in std cells GDS have floating bulks while their schematics have bulks correctly connected. So how Nangate give out a cell library with cells that is not correctly connected ? (I knew this from performing LVS check on one std cell from this library)
Am I supposed to specify anything in "Place" tab in SoC Encounter (maybe Physical Cells or Tie HI/LO) to tie the transistor bulks ?
Any thoughts ?