floating transistor bulks in a Standard Cell Library

[oAwad]

Hello all,

I want to know if it's normal for std cell libraries to have their std cells with non-tied bulk transistors. I'm using Nangate 45nm library and found that transistors in std cells GDS have floating bulks while their schematics have bulks correctly connected. So how Nangate give out a cell library with cells that is not correctly connected ? (I knew this from performing LVS check on one std cell from this library)

Am I supposed to specify anything in "Place" tab in SoC Encounter (maybe Physical Cells or Tie HI/LO) to tie the transistor bulks ?

Any thoughts ?

 

[oratie]

Such library (tapless) should contains special cell (tap-cell), which connect bulk to VDD/VSS. You should place this cell with pre-defined pitch across all you std.cell area. It should be stated somewhere in datasheet or app. guide.

 

[oAwad]

Such library (tapless) should contains special cell (tap-cell), which connect bulk to VDD/VSS. You should place this cell with pre-defined pitch across all you std.cell area. It should be stated somewhere in datasheet or app. guide.

Thanks for your reply. I didn't find any tap-cells in the library datasheet, but on Nangate's website I found that they added taps to all Filler cells. Does this mean that Filler cells now act as tap-cells as well ? I already added Filler cells to my design (place > physical cells > add filler), but you can see from LVS result below that bulk "b" in layout is connected to a floating net (net 7) and not VDD.

DISC# LAYOUT NAME................................... SOURCE NAME
**************************************************************************************************************

3 M5(0.525,0.680) MP(PMOS_VTL) ................... M_i_1 MP(PMOS_VTL)
g: 8 .................................................... g: ZN_neg
s: ZN .................................................. s: ZN
d: VDD .................................................. d: VDD
b: 7 ................................................... ** no similar net **
** VDD ** ............................................ b: VDD

I can see the Filler cells as the only option in the "add well tap" window, so should I add the Filler cells again as (place > physical cells > well tap) ?

 

[oratie]

It is possible, that fillers act as tap-cell. You should check, that every std cel rows contains fillers. Also, check that all fillers have taps. Maybe some very small fillers have not tap inside due to cell area limitation?

Anyway, I did not work with nangate library, it is better check with their docs.

 

[ThisIsNotSam]

Thanks for your reply. I didn't find any tap-cells in the library datasheet, but on Nangate's website I found that they added taps to all Filler cells. Does this mean that Filler cells now act as tap-cells as well ? I already added Filler cells to my design (place > physical cells > add filler), but you can see from LVS result below that bulk "b" in layout is connected to a floating net (net 7) and not VDD.

DISC# LAYOUT NAME................................... SOURCE NAME
**************************************************************************************************************

3 M5(0.525,0.680) MP(PMOS_VTL) ................... M_i_1 MP(PMOS_VTL)
g: 8 .................................................... g: ZN_neg
s: ZN .................................................. s: ZN
d: VDD .................................................. d: VDD
b: 7 ................................................... ** no similar net **
** VDD ** ............................................ b: VDD

I can see the Filler cells as the only option in the "add well tap" window, so should I add the Filler cells again as (place > physical cells > well tap) ?

This is pretty common in std cell libraries. Fillers act as double purpose cells.