Floating/ Fixed point in VHDL

[n_sanjay_n]

Hey everyone,

I want to implement an equation involving heavy fixed point math. I have posted the code below.

The problem: I want to form the equation in the for loop. To do that, I must declare a 2D array for both "dv" and "v".
I tried using a type declaration statement, but works only inside an architecture (trouble for declaring dv).

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Code VHDL - [expand]
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library floatfixlib;
use floatfixlib.math_utility_pkg.all;
use floatfixlib.fixed_pkg.all;
 
entity xxx is
port(Ie: in sfixed(17 downto -110);
dv: inout sfixed);------Here's the problem
end xxx;
 
 
architecture neu of xxx is
type dataout is array (6 downto 0,11 downto -55) of sfixed;------this declaration is after dv is defined...so dv is of unknown format!!!!
signal Cm, Gl, Gl_Cm, El, A, dt: sfixed(8 downto -55);
signal v: dataout; 
begin
 
Cm <= to_sfixed(0.0000000002, Cm);
Gl <= to_sfixed(0.00000001, Gl);
Gl_Cm <= to_sfixed(0.02, Gl);
El <= to_sfixed(-0.07, El);
A <= to_sfixed(0.000000002, A);
dt <= to_sfixed(0.00646, dt);
 
v(0) <= to_sfixed(0, v(0));
dv(1) <= ((Gl_Cm*El)+(Ie/(A*Cm)))*dt;
v(1) <= v(0)+dv(1);
 
process(dv, v)
begin
for i in 2 to 1500 loop
dv(i) := (Gl_Cm*(v(i-1))+(Gl_Cm*El)+(Ie/(A*Cm)))*dt;-------is this for loop declaration correct????
v(i) := v(i-1)+dv(i);
end loop;
end process;
end neu;

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Can someone help me out????

 

[K-J]

Can someone help me out????

The type declaration should be moved to a package that you then use prior to the entity declaration. Something like this...

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Code VHDL - [expand]
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package pkg_xxx is
   type dataout is array (6 downto 0,11 downto -55) of sfixed;-- Now the data type is defined in a package
   end pkg_xxx;
use entity work.pkg_xxx.all;
entity xxx is
... 
dv: inout dataout); -- This is the type you want for dv correct?
...
signal v: dataout

---

Kevin Jennings

 

[n_sanjay_n]

Hi,

I tried creating a new package. This is giving a new error: [Array element type can not be unconstrained array type floatfixlib.fixed_pkg.unresolved_sfixed].
While compiling the package definition i.e at line 2 of the code you have shown above.

 

[permute]

yes, there are several issues with your code.

VHDL has a concept of "unconstrained" types, which are commonly used for functions. eg "bit_reverse" might take just a "std_logic_vector" as an argument. The size would be determined using x'range, x'high, x'low, etc... unsigned/signed/ufixed/sfixed also can work this way.

The issue is that there isn't anything that allows the tools to determine the size of this 2 dimensional array of sfixed. more likely, you wanted a 1d array of sfixed(11 downto -55).

The code is also technically synthesizable, but would infer several thousand multipliers. More than exist on any single FPGA at this time. This would result in a failure to actually build the design outside of simulation. you likely want to use a clocked process that uses a smaller number of multipliers and takes a thousand cycles or so to compute a result.

next, signals don't have a blocking assign. You'd need to use variables within the process and assign the results of the for loop to the correct signals.

finally, why is dv an inout?

 

[n_sanjay_n]

Hi,

Thanks for the heads-up. I am doing this as a start. I would use a more optimized version for actual implementation.
About the 2D array, is it possible with sfixed as the datatype???

dv is an inout signal because I am reading previous value of dv(i-1) on the RHS and updating the current value in location dv(i) on the LHS.
If I use a out signal, I would not be able to read it into the code again.

Actually, you are quite right about the speed. It takes nearly 4 hrs to simulate 3 seconds (realtime) of the model.

Please let me know if there is any way to declare the 2D array.

Thanks

 

[FvM]

According to your requirement, a buffer port type would allow to read back the output state.

I don't get yet the purpose of the design. Simulating non-synthesizable HDL code, except for test benches, seems pretty pointless in my view.

 

[K-J]

Thanks for the heads-up. I am doing this as a start. I would use a more optimized version for actual implementation.
About the 2D array, is it possible with sfixed as the datatype???

Assuming you mean a single dimensional array of sfixed arrays, then it would be
type dataout is array (6 downto 0) of sfixed(11 downto -55);

If you really do want a two dimensional array of sfixed, then you need to specify the precision of the sfixed type that you want to use and the declaration would be...
type dataout is array (6 downto 0,11 downto -55) of sfixed(??? downto ???); -- ??? to be defined by you.

dv is an inout signal because I am reading previous value of dv(i-1) on the RHS and updating the current value in location dv(i) on the LHS.
If I use a out signal, I would not be able to read it into the code again.

In that case, 'dv' can't be an inout or buffer. 'Current' and 'next' values of 'dv' must be different signals.

Kevin Jennings

 

[permute]

For simulation, what you want is to have variables in the process for dv, dv_prev, etc... After the for loop, these would be assigned to the signals/ports. Simulations tend to favor variables over signals. That said, the logic is the same and would infer several thousand multipliers in actual hardware. This makes either coding style effectively unsynthesizable.

 

[n_sanjay_n]

Hey,

Thanks for the advice. The package definition now works, but like permute pointed out, the inout does not work. I will keep u posted on my progress.

BTW, I found out that librarys have to be defined again in the following way:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library floatfixlib;
use floatfixlib.math_utility_pkg.all;
use floatfixlib.fixed_pkg.all;

package pkg_xxx is
   type dataout is array (1547 downto 0) of sfixed(147 downto -237);
   end pkg_xxx;
use work.pkg_xxx.all;

library floatfixlib;
use floatfixlib.math_utility_pkg.all;
use floatfixlib.fixed_pkg.all;