FIR on FPGA(DSP48) an urgent question

[alimassster]

dsp48

Hello friends
Imagine x as a continuous stream of input samples and y as a resulting stream
the sample delay logic is denoted by Z^-1, where the -1 represents a single clock delay.The delayed input samples are supplied to one input of the multiplier.coefficients (denoted by h0 to h(N-1)) are supplied to the other input of the multiplier Y is merely the summation of a set of input samples.

Now my question

Cascading dsp48 blocks , how many clocks do we need to have a result in the output ?
And by cascading such these blocks if we need for example N clocks to feed multipliers with N inputs in an N tap FIR filter to calculate Y , then what's the difference between the parallel form and a single MACC based form ( there's an equal delay(number of clocks) in both forms)?
thx

 

[Sathish]

dsp48 fir

hi alimasster,
If i am right, the clock required to get the output y will depend of the algorithm of the multiplier used and 'N'. (The multiplier has to finish the multiplication operation(input with h) before the next input comes.)

If you get better idea please don't forget to share with me.


with regards
sathish kumar

 

[alimassster]

dsp48 fir filter

thanks for your regard
I just wanna know by cascading DSP48 blocks if we need for example N clocks to feed multipliers with N inputs in an N tap FIR filter to calculate Y , then what's the difference between the parallel form and a single MACC based form ( if there's an equal delay(number of clocks) in both forms)?

what's the advantages of parallel implementation?
I know in parallel form we have a result in every clock cycle.
but is it because of useing pipeline or something else?

Are inputs ( not coeficients ) fed into multipliers simultaneously or one by one by using BCIN-BCOUT ? if so , again what's the advantage of a parallel form? is it using a pipeline or what?

Thx in adv
Have a nice time
Master