H.Hachem
Junior Member level 3
Hello,
I'm trying to implement an FIR filter in Verilog and was wondering, if there's any practical way to truncate/round the MAC outputs in order to get the same output bit length as the input. I would simply round the output of the filter to the nearest quantization level, but maybe someone has a better idea.
Ans how about when using multistages, e.g. CIC-CIC-FIR-CIC-CIC . Should I apply bit pruning to every CIC stage or simply round at the very end of the chain?
Thanks in advance
I'm trying to implement an FIR filter in Verilog and was wondering, if there's any practical way to truncate/round the MAC outputs in order to get the same output bit length as the input. I would simply round the output of the filter to the nearest quantization level, but maybe someone has a better idea.
Ans how about when using multistages, e.g. CIC-CIC-FIR-CIC-CIC . Should I apply bit pruning to every CIC stage or simply round at the very end of the chain?
Thanks in advance