cyboman
Member level 4
since i'm somewhat new to digital design and code in verilog i decided to take a look at vhdl. as far as i understand it is a very strongly typed language.
i understood that signals of type std_logic and std_logic_vector can take on the values of 1, 0, u, x, and z, but what about the following types
unsgined
signed
natural
integer
boolean
for that matter, since any hdl is used to model a digital circuit why do we need so many types of variables? aren't all of them just boolean type? maybe someone can give an example where i would use singed type as opposed to std_logic or unsgined as opposed to std_logic_vector
any help is appreciated
i understood that signals of type std_logic and std_logic_vector can take on the values of 1, 0, u, x, and z, but what about the following types
unsgined
signed
natural
integer
boolean
for that matter, since any hdl is used to model a digital circuit why do we need so many types of variables? aren't all of them just boolean type? maybe someone can give an example where i would use singed type as opposed to std_logic or unsgined as opposed to std_logic_vector
any help is appreciated