ESD vs Cold Spare capability in IO pads

[Kirr]

Hello everyone.
Now i'm working on unidirectional input pad with cold spare capability. That means i have to manage gate and well connections of PMOS ESD diode to exclude leakage current through drain-well and drain-source when Vcc is floating and Vpad>Vcc. Simultaneously there should be ESD-protection through PAD to VCC, i.e. opportunity to drain the current impulse to VCC.
I know how to resolve the first task with cold spare, but i don't really understand how to realize these two capabilities simultaneously, because in the first case we shouldn't drain the current through PAD->VCC but in the second we should.
Please help me to resolve this contradiction. Thanks in advance.

 

[D.A.(Tony)Stewart]

Does this help?
https://www.altera.com/en_US/pdfs/literature/wp/wp_hsfeat.pdf

 

[dick_freebird]

First, is your ESD diode really a PMOSFET? Or is it
in fact a plain diode, or a PNP (P+ in Nw in Pepi)?

Eliminating the "up" diode is common in both space
parts (which highly prize cold sparing ability) and in
some industrial parts as well. In this case, now you
need to provide an alternate path for the pin overstress
current.

Schemes involving parallel ESD rings, and treating the
vss and vdd rails as simply "other inputs", permits cold
sparing so long as you don't mind some extra leakage
when your pin in question, is the one biasing the ring
to its outermost voltage.

Star clamp schemes, where each pin returns to the
"ground" ring (which could be global vss / substrate,
or could be an explicit protection ground) will make
each pin independent of (positive) voltage activity
on the rest. The cost here is one breakdown (or
commutated) clamp per pad so-protected. I've done
many designs this way. However I've also found that
modeling weasels care not one bit about accurately
modeling breakdown, snapback and post-snapback
impedance of the pin, all of which matter if you
want to, you know, actually -design- ESD protection
rather than taking a blind stab or cookbook approach
(and when you are the first out of the gate, no
cookbook exists for you).

I advise you to begin by locating your positive-stroke
clamp options, drawing cross-sections of each and
getting your mind right about their true nature and
action. Then, on to assessing the validity of the
models you're provided against real material (TLP
measurements, for pulsed overvoltage response).
From this you can augment toe models to be as
realistic as they need to be, and have yourself a
time designing ESD protection networks that work
under your set of normal and abnormal conditions.

 

[Kirr]

Yes, my ESD diode is simple PMOSFET.
Star clamps is very interesting solution, but i can't imagine the circuit, could you give some examples?