[SOLVED] ESD.18g DRC error in I/O cells

[stevenv07]

Hello everyone,

When I checked DRC for the whole chip (TSMC 28nm), two ESD drc errors happen (ESD.18g and ESD.19g). These errors relate to finger width of NMOS and PMOS in ESD circuits of I/Os. I don't know how to solve it. Could you please help me on this? The attached is the error description in Calibre rule

Thanks in advance!
Steve

 

[dick_freebird]

It appears that they want a larger (wider)
device than you have placed. Clamp width
goes directly to HBM ESD voltage rating. Add
a finger, or just add a bit of finger-W since
you're fairly close (to the rule; the ESD goal,
we do not know).

 

[ThisIsNotSam]

check the documentation for waivers. TSMC IO cells are known for not respecting their own rules.

 

[stevenv07]

check the documentation for waivers. TSMC IO cells are known for not respecting their own rules.

I checked the document of TSMC IO cells, but there is no statements for waivers.

Thanks,
Steve

 

[ThisIsNotSam]

did you check a sneaky .txt file that comes with the release notes? This info is usually hidden in there...

 

[stevenv07]

did you check a sneaky .txt file that comes with the release notes? This info is usually hidden in there...

Thank you so much. I just found it in the release note as you said. This DRC error can be waived.

Steve.