Kaka_fsk
Newbie level 5
I am trying to synchronize an asynchronical control signal using the following verilog code:
input clk;
input start;
output start_real;
reg [3:0] start_shift;
always@(posedge clk)
begin
start_shift <= { start_shift[2:0], start };
if (start_shift == 4'b1111)
start_real <= 1'b1;
else
start_real <= 1'b0;
end
I think four registers are enough to debounce the signal. But the post-place simulation still report error about setup time violation(see the image).
Could anyone give me some suggestion? Thanks in advance.
input clk;
input start;
output start_real;
reg [3:0] start_shift;
always@(posedge clk)
begin
start_shift <= { start_shift[2:0], start };
if (start_shift == 4'b1111)
start_real <= 1'b1;
else
start_real <= 1'b0;
end
I think four registers are enough to debounce the signal. But the post-place simulation still report error about setup time violation(see the image).
Could anyone give me some suggestion? Thanks in advance.