error when synchronizing a asynchronical signal

[Kaka_fsk]

I am trying to synchronize an asynchronical control signal using the following verilog code:

input clk;
input start;
output start_real;

reg [3:0] start_shift;

always@(posedge clk)
begin
start_shift <= { start_shift[2:0], start };
if (start_shift == 4'b1111)
start_real <= 1'b1;
else
start_real <= 1'b0;
end

I think four registers are enough to debounce the signal. But the post-place simulation still report error about setup time violation(see the image).


Could anyone give me some suggestion? Thanks in advance.

 

[ring0]

Is the input signal changed simultaneously with the clock signal in your testbench?

Synchronizing registers are useful when running design in hardware, but during simulation such thing won't help you. So maybe you shouldn't bother yourself with this problem.

 

[Kaka_fsk]

Thanks for your reply, Ring0.

The input violate the setup time according to the error report.

Do you mean the post-route simulation can't take the debouncer into account, even in real life it works?

Thanks.

 

[rberek]

Well, the setup time is being violated, so the simulator is complaining. It is not intelligent enough to guess that your circuit is there for clock domain crossing purposes. It just sees a netlist and makes no assumptions about what you were trying to do.

You either have to turn off timing checks or ignore the errors.

r.b.