Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

error on VHDL program....

Status
Not open for further replies.

energy_baz

Junior Member level 1
Joined
Nov 24, 2010
Messages
18
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,413
hi,

could anyone help me to fix this error...the error state : Found 0 definitions for operator "+"...thanks :)
 
Last edited:

wire1(n) is a std_logic. wire1(n downto n) is a 1 bit unsigned value. "+" is not defined for unsigned+std_logic, but for unsigned+unsigned (and unsigned+integer).
 

so, I have to convert wire1(n) into unsigned/integer is it..?
 

try using wire1(n downto n) for a 1 bit unsigned array, and it should work.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top