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I don't know if I really understand what you are trying to say but if you are asking what is the n/p epi's function in your stated stack up, for an npn transistor, the n-epi will serve as the collector region of the device. For a substrate vertical pnp and a lateral pnp, the n-epi will serve as the base region of the device. When the epi region is p-epi, this can be channel for an nmosfet, it can be part of a junction capacitors/diodes, or an isolation ring if the p-epi is doped heavy.
In BiCMOS, the epi layer allows for a highly doped substrate on which a lighter doped epi is grown. The lighter doped epi allows standard cmos to be built in the epi region using conventional N-Wells and if necessary P-Wells for twin well cmos.
This would not be possible on highly doped substrates. Now you have a thin epi in which all the cmos is build you can use deep N+ (for highly doped N substrates) or deep P+ (for highly doped P+ substrates) to connect from the top of the epi to the substrate. This allows for good noise isolation in addition to vertical BiPolars. It can also allow for very high voltage vertical devices such as DMOS devices (upto 1200V have been done)
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