Dynamic Phase Shift issue for spartan-6

[promach]

I enabled Dynamic Phase Shift Ports inside ISE clocking wizard coregen, however I have the following issues about unsupported frequencies marked as XXX in the table:

100MHz, 200MHz, 300MHz, 400MHz, 500MHz are all not supported when Dynamic Phase Shift is enabled.

Note: I am using 50MHz source clock

 

[FvM]

Just a matter of limited Xilinx series 6 clocking features. If you read the documentation thoroughly, you'll notice that dynamic phase shift and clock multiplication (DFS) are mutual exclusive DCM options.

 

[bansalr]

if you can use two DCM one for clock multiplication and other for dynamic phase shifting .... since the Dynamic phase shifting is using delay TAPS ...it's not a part of clock multiplication circuitry ....as shown above...

 

[promach]

@bansalr

DCM IP is not available to spartan-6, do you mean two PLL IP instead ?

As for "Dynamic phase shifting is using delay TAPS", do you mean I should use separate IODELAY primitive instead of PLL ?

 

[bansalr]

yes, If you can use two PLL IP instead ... No I am explaining how dynamic phase shift works using delay inside the IP...

 

[promach]

In xapp1064 , why is PLL needed in Figure 5 , but not needed in Figure 6 ?