Dutied Control Singal Generation

[ChickenPork]

Hi, I'd like to make a control signal that is enabled during the clock falling and turned off before the clock rises.

I tried to make control signals A & B, but i have difficulty making them.

Rules are
1. All signals (including clk) should not overlap
2. A & B are ratioed with respect to CLK. (i.e. A & B's duty is 20% compared to CLK, so whenever CLK frequency changes, A & B should also changes)
3. It's allowed that there exist master clock (i.e. CLK is divided from master clock at least 100 times)

Thank you in advance.

 

[ThisIsNotSam]

Are you making a design that has this behavior or a testbench that generates this behavior?
- the first is not entirely possible with code. this is not how RTL works, you don't have such fine degree of control within a clock cycle. you would need at least two clocks to get anything reasonable. but this means the second clock would have to be many times faster than the first one, which again is not a reasonable assumption.
- the latter is very possible with time control statements like the # operator in Verilog.

 

[BradtheRad]

4017 IC (decade counter) is ideal for this job. Apply a pulse train at ten times the frequency of your desired final frequency.
Merge the first 5 outputs (through diodes) to create your first clock. Duty cycle is 50%.
Pin 7 is A. Pin 9 is B. The remaining three outputs (6, 8, 10) are unused.

A & B length automatically equal 20% of first clock.
No signals overlap.

 

[ThisIsNotSam]

4017 IC (decade counter) is ideal for this job. Apply a pulse train at ten times the frequency of your desired final frequency.
Merge the first 5 outputs (through diodes) to create your first clock. Duty cycle is 50%.
Pin 7 is A. Pin 9 is B. The remaining three outputs (6, 8, 10) are unused.

A & B length automatically equal 20% of first clock.
No signals overlap.

sure, but that would be a discrete component that does that. I thought the question was more like how to design said discrete component, given that this is the ASIC subforum

 

[ChickenPork]

Are you making a design that has this behavior or a testbench that generates this behavior?
- the first is not entirely possible with code. this is not how RTL works, you don't have such fine degree of control within a clock cycle. you would need at least two clocks to get anything reasonable. but this means the second clock would have to be many times faster than the first one, which again is not a reasonable assumption.
- the latter is very possible with time control statements like the # operator in Verilog.

Thank you for your reply. Your first answer on non-overlapping signals helps me. But for the second question, a suggestion on the # operator, I want to make it synthesizable, so isn't it impossible to use the # operator?

 

[ChickenPork]

4017 IC (decade counter) is ideal for this job. Apply a pulse train at ten times the frequency of your desired final frequency.
Merge the first 5 outputs (through diodes) to create your first clock. Duty cycle is 50%.
Pin 7 is A. Pin 9 is B. The remaining three outputs (6, 8, 10) are unused.

A & B length automatically equal 20% of first clock.
No signals overlap.

Thank you but as @ThisIsNotSam said, I want to make it synthesizeable

 

[BradtheRad]

I see a hint in the rule (#3) specifying a master clock whose frequency is several times the resulting output frequency. This suggests some kind of counting strategy is the path to success.

The 4017 IC contains several Johnson counters. I suppose you can build an equivalent made from flip-flops.
Or... your counter can be assembled from full adders (each requires a few logic gates). Send it through a DAC. Drop its output voltage to 20% via resistor divider. This voltage is a target value for a second counter used in creating waveforms A & B. Whatever the length of the first waveform, A & B will be 20% of it.

There's also the idea of capacitive charge bucket, possibly combined with a sample-and-hold circuit.

I don't know just where the line is between synthesizable versus not.

 

[KlausST]

Hi,

to me it´s not clear.

You say you tried to generate A and B. But what about CLK?

Is CLK an input (1) , or do you have to generate CLK (2)?

In other words (related to the 100x CLK)
is it:
(1): CLK --> PLL (x100) --> MCLK ?
or
(2): MCLK --> divider (/100) --> CLK?

You also say: "Whenever CLK frequency changes" ....
So "who" changes the frequency?

The problem I see:
If CLK is an external signal (input), and it´s frequency changes, then you can´t know beforehand hen will be the rising edge (unless you can look into the future).
Thus the requirement "A nd B signals need to be OFF BEFORE rising edge of CLK is impossible to achieve without additional informations.
(sweep timing, frequency range, jitter...)


Klaus

 

[ChickenPork]

Hi,

to me it´s not clear.

You say you tried to generate A and B. But what about CLK?

Is CLK an input (1) , or do you have to generate CLK (2)?

In other words (related to the 100x CLK)
is it:
(1): CLK --> PLL (x100) --> MCLK ?
or
(2): MCLK --> divider (/100) --> CLK?

You also say: "Whenever CLK frequency changes" ....
So "who" changes the frequency?

The problem I see:
If CLK is an external signal (input), and it´s frequency changes, then you can´t know beforehand hen will be the rising edge (unless you can look into the future).
Thus the requirement "A nd B signals need to be OFF BEFORE rising edge of CLK is impossible to achieve without additional informations.
(sweep timing, frequency range, jitter...)


Klaus

My problem definition was not straightforward.

Actually, the clock generation mechanism is (2) in your answer.

There's an external master clock (MCLK), which is fixed, and I divide it to get CLK.

So my 'CLK frequency changes' means division ratio changes.

I have the ability to change the division ratio.

For example, when MCLK = 100MHz, I make CLK like 1MHz and 100kHz.

So whenever CLK changes, I want to make A & B's turn on time like (1/1MHz) * 0.2 or (1/1kHz) *0.2

For the simplicity, just ignore my rule #1 about non-overlapping signal.

 

[KlausST]

Hi,

OK, then it´s simple:
It´s basically just a counter-and-compare problem

Let´s say the counter goes from 0 to 99.
Then
* CLK falling at 0
* CLK rising at 50
* A rising at 1
* A falling at 24
* B rising at 25
* B falling at 49

Klaus

 

[danadakk]

https://athena.ecs.csus.edu/~pheedley/ADC_team_docs/ADC2_clkgen_arch_review.pdf

Creating skew : https://stackoverflow.com/questions/57202757/how-to-phase-clock-in-system-verilog

Post #12 https://www.edaboard.com/threads/no...h-same-frequencies-as-the-input-clock.389235/


Regards, Dana.

 

[ThisIsNotSam]

if you are allowed to have two clocks, then it is easy. use a few counters and you are done, all coded in RTL, no need for exquisite analog-ish solutions

 

[ChickenPork]

if you are allowed to have two clocks, then it is easy. use a few counters and you are done, all coded in RTL, no need for exquisite analog-ish solutions

https://athena.ecs.csus.edu/~pheedley/ADC_team_docs/ADC2_clkgen_arch_review.pdf

Creating skew : https://stackoverflow.com/questions/57202757/how-to-phase-clock-in-system-verilog

Post #12 https://www.edaboard.com/threads/no...h-same-frequencies-as-the-input-clock.389235/


Regards, Dana.

Hi,

OK, then it´s simple:
It´s basically just a counter-and-compare problem

Let´s say the counter goes from 0 to 99.
Then
* CLK falling at 0
* CLK rising at 50
* A rising at 1
* A falling at 24
* B rising at 25
* B falling at 49

Klaus

Thank you so much. I think I can make it

 

[D.A.(Tony)Stewart]

20 % d.f. with 2 cascaded synchronous stages implies you could use a 5x Clock and logic and 5 stage shift register with POR preset with no PLL as a "Ring counter"

You can start with that and make a truth table. Then make the f(input) /5 as your output clock which is delayed (async ) more than Q4,Q5 synchronous outputs on 5 stage ring counter. f/5 clk out can be just an RS latch for Q6. Simulation= https://tinyurl.com/yu8zbkqo

The trick here is the async. divide by 5 clock is 2.5 half cycles state controlled with a parallel Power On reset (POR) of 00100.

Binary count and compare must obey the async delays of gates to ensure non-overlapping edges depending on your setup and hold requirements.