Dual Port ram Simulation Issue

[shethpurak]

Hi

This is how I have implemented my dual port ram

always@(posedge clk) begin
if(wr_en)
mem[wr_ptr] <= data_in;

end

always@(posedge clk) begin
if(rd_en)
data_out <= mem[rd_ptr];

end


Somehow in the simulations my data_out is 1 clock delayed. it gets output after 1 clock delay after rd_en.

I know one is use asynchronous read using assign statements. Is there any solutions with keeping the read synchronous so that my read happens at the same time I get the rd_en.

Please let me know

Thanks

 

[rakko]

do it like this:

always @(*)
if (rd_en)
data_out_pre =mem[rd_ptr];


always@(posedge clk)
data_out <= data_out_pre;

Basically, you are reading the ram with combo logic and transfer it to the output on clock edge.

 

[HolySaint]

I do like shethpurak,but when i sim the netlist syn by dc,read happens at the same time I get the rd_en.
I use "<=" .

 

[lostinxlation]

Why don't you just do this ?

always@(posedge clk) begin
if(wr_en)
mem[wr_ptr] <= data_in;

end

assign data_out = rd_en ? mem[rd_ptr] : z ;


This is actually a synchronous read as long as rd_en is synchronizing the read clock.