DSP48E1 vs DSP48A1 double float adder

[hornysquid]

Hello. I am now using floating-point IP generator in Xilinx ISE to generate double float adder. For Spartan-6, it only makes use of LUTs, while on 7 Series it is possible to utilize DSP48E1. Please explain to me, is there any fundamental difference between these DSP types that makes it impossible to utilize DSP48A1 on Spartan-6? Thank you.

 

[dpaul]

7 Series DSP48E1 Slice-
https://www.xilinx.com/support/documentation/user_guides/ug479_7Series_DSP48E1.pdf

Spartan-6 FPGA DSP48A1 Slice-
https://www.xilinx.com/support/documentation/user_guides/ug389.pdf

The user guides should tell you the differences.

 

[hornysquid]

The point I am trying to make is: as long as there is DSP block, there should be a way to implement floating-point adder, but for some reason Xilinx didn't make it, and I wonder why.

 

[vGoodtimes]

Not sure. The floating point add should be a few compares, a barrel shifter, and an adder IIRC. I don't see anything in th DSP48E1 that makes it seem better at this.