doubts regarding vhdl coding

[M.Shobana]

hi........

what is the use of generic declaration in vhdl? is there any possibility of using memory lesser than the allocated memory?
for example : if iam declaring as qut std_logic_vector(3 downto 0) can i use 2 bits instead of it without modifying the coding?iam doing project work so send me the solution as soon as possible

 

[prakashvenugopal]

HI,

Generics are used in order for u to be able to declare constants in
the design in a generic way
e.g. -

entity adder is
generic (bus_width : integer := 8 ;
Port ( a: in std_logic_vecor (bus_width-1 downto 0);
b: in std_logic(bus_width-1 downto 0);
res : out std_logic(bus_width downto 0));
end adder ;

 

[TrickyDicky]

generics can also be used to completly change designs and architectures. But like prakashvenugopal said, they are constant and so do not change while the code is running.

 

[M.Shobana]

thank u sir........
my another question is: in my program no of bits in output is undetermined becuse output depends on the i/p and calculation it may vary based on number of inputs while v r giving n simulation .in tis situation how cn i declare output size

 

[prakashvenugopal]

Hi,

What is your maximum value for the Input and output.? I will declare the Max. value for both inputs and outputs.

 

[TrickyDicky]

you always size the input and output based on the worst case. The size of the ip and output cannot change.

 

[M.Shobana]

case state is
when s1=>
if(x(1)==0) then
nextstate<=s2;
q1<="001";
else
nextstate<=sin;
q1<={q0,"000"};
end if;
in this program we may have the size of q as either 3 0r 6 bits. finally we have to concatenate all the 15 values of q1,q2,.......q15 in z; then how we can initiallize the size of q and z?