doubts in vhdl coding

[M.Shobana]

hi.......
case state is
when s1=>
if(x(1)==0) then
nextstate<=s2;
q1<="001";
else
nextstate<=sin;
q1<={q0,"000"};
end if;
in this program we may have the size of q as either 3 0r 6 bits. finally we have to concatenate all the 15 values of q1,q2,.......q15 in z; then how we can initiallize the size of q and z?

if anybody knws solution for the above pblm means plz reply me quickly

 

[Marcel Majoor]

I have a problem with interpreting your question ...
What 'q', 'z'. A signal with different sizes?

But, you probably are looking for the something that concatenates all the (remaining) bits of a vector. Use 'others' for this.

z <= (others => '0');
z <= (others => '0', q);

Also, see
**broken link removed**