vikas_33
Junior Member level 2
Hi,
In our design we r generating 1MHZ clock from 8mhz clock.
There are some logic in design where we are sending data from 8Mhz to 1 MHZ.
Do we need to set multicyle paths for setup and hold check?
Thanks
In our design we r generating 1MHZ clock from 8mhz clock.
There are some logic in design where we are sending data from 8Mhz to 1 MHZ.
Do we need to set multicyle paths for setup and hold check?
Thanks