[SOLVED] does verilog have a main?

[kenleigh]

Where the program execution start?

My top level module looks like this?

module test( CLK_INP1, CLK_OUTP1, RST, LOCD);
 
  input CLK_INP1, RST;
  output CLK_OUTP1, LOCD;
 
// INST_TAG
  clk_wiz_v1_5 camclk
   (// Clock in ports
    .CLK_IN1            (CLK_INP1),    // IN
    // Clock out ports
    .CLK_OUT1           (CLK_OUTP1),    // OUT
    // Status and control signals
    .RESET              (RST),        // IN
    .LOCKED             (LOCD));      // OUT
// INST_TAG_END

endmodule

How do I make this run?
Will the simulator or synthesis tool automatically configure this as my starting point?
Do I have to instantiate this module?

 

[amitjagtap]

What is this actually A IP core Code.... or the code that you have written....
If i m not wrong this is the IP code..

 

[kenleigh]

What is this actually A IP core Code.... or the code that you have written....
If i m not wrong this is the IP code..

The test module instantiates the IP core generated by Core Generator, it uses a PLL_BASE primitive, I haven't pasted that code here for legibility.

 

[amitjagtap]

Well if that is the case you can directly simulate this....
Assign pins (Spartan 100MHz clk to CLKIP and CLK I/O capable pin to ClKOUT ) and synthesize it.

 

[kenleigh]

Well if that is the case you can directly simulate this....
Assign pins (Spartan 100MHz clk to CLKIP and CLK I/O capable pin to ClKOUT ) and synthesize it.

And how do I do that, what syntax do I use?
Also what is the execution start point in Verilog?

 

[mashhur]

just set it as a top module.. i've running on Xilinx ISE.

 

[kenleigh]

just set it as a top module.. i've running on Xilinx ISE.

How to set it as top module? Does program execution always start at top module?

 

[TrickyDicky]

There is no program execution in HDL. It is descibing hardware where all parts run in parallel.