alard
Member level 4
veriloga genvar not supported
Hello,
I wrote a short code to simply handle my input signal. It can pass the compilation but the output waveform is really strange. If I don't use vector but list all the ports one by one, it works which means the code itself functions well.
In addition, I also tried to use "for" to gernerate the outputs but seems unable to pass the compiler.
Could someone take a look at the code below?
-----------------------------------------------------------
`include "constants.h"
`include "discipline.h"
module RZ_Generator(vin, vout, clk, offset);
input clk, offset;
voltage clk, offset;
input [11:0] vin;
output [11:0] vout;
voltage [11:0] vin, vout;
integer i;
analog begin
//for(i=0; i<=11; i=i+1) begin
//V(vout) <+ V(vin)*V(clk)+V(offset);
//end
generate i (11, 0) begin
V(vout) <+ V(vin)*V(clk)+V(offset);
end
end
endmodule
-------------------------------------------------------------
Best Regards,
Hello,
I wrote a short code to simply handle my input signal. It can pass the compilation but the output waveform is really strange. If I don't use vector but list all the ports one by one, it works which means the code itself functions well.
In addition, I also tried to use "for" to gernerate the outputs but seems unable to pass the compiler.
Could someone take a look at the code below?
-----------------------------------------------------------
`include "constants.h"
`include "discipline.h"
module RZ_Generator(vin, vout, clk, offset);
input clk, offset;
voltage clk, offset;
input [11:0] vin;
output [11:0] vout;
voltage [11:0] vin, vout;
integer i;
analog begin
//for(i=0; i<=11; i=i+1) begin
//V(vout) <+ V(vin)*V(clk)+V(offset);
//end
generate i (11, 0) begin
V(vout) <+ V(vin)*V(clk)+V(offset);
end
end
endmodule
-------------------------------------------------------------
Best Regards,