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distributed power amplifier

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padoh

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ive designed a distributed LNA..but as i place the input coupling cap of 50p or greater or infact any capacitor at the i/p, my gain becomes negative? can anyone plz suggest where is the problem in the design? the o/p coupling cap works fine
 

Present a schematic and specify frequency range of your input signal. Otherwise it's just guessing?
 

Present a schematic and specify frequency range of your input signal. Otherwise it's just guessing?

its kind of confidential..can u just specify some of the reasons tht might be the causes.. frequency from 100M to 2G..plz it would be a great help..m just stuck up..
 

Ok, which technology, bipolar or mos? Or maybe it is possible that you roughly depicts the input stage not the complete lna? What happen if you use smaller values for your cap?
 

Ok, which technology, bipolar or mos? Or maybe it is possible that you roughly depicts the input stage not the complete lna? What happen if you use smaller values for your cap?

CMOS 130nm..i just applied a 500f cap n even then the gain is negative ..upto several micros of capacitance, the gain is still negative..its a three staged cascoded DA with inductive degenration..a transmission line at the input..

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ive attached a ppr..plz see fig2..my design is almost the same( the input path connecting the lower transistors of the cascode)..i am just missing the capacitor Cb..what effect can this have on the circuit gain?

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ive attached a ppr..plz see fig2..my design is almost the same( the input path connecting the lower transistors of the cascode)..i am just missing the capacitor Cb..what effect can this have on the circuit gain?
 

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  • payam heydari...distributed lna2007.pdf
    1.4 MB · Views: 59

Are you blocking maybe some dc bias voltage at the gate, despite I don't see any bias in fig.2, but maybe in your design! And be careful with uploading ieee documents, i think it is not allowed.
HTML:

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Now I see on the right side some dc path, again: are you blocking maybe this voltage?
 

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