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it's better if u can use a DDC at the front end b4 demodulation to convert this IF to baseband or very near to the baseband. B/w of 3.5Mhz is not a problem for an FPGA to perform a QPSK demodulation.
what is the data rate required?
if you use 70Mhz sampling clock, the sampled signal's negative spectrum will be alias with positive spectrum, and you will not demodulate your PSK signal.
if you use 60M-65Mhz sampling clock, the sampled digital signal's main spectrum will be located in 10M-20MHz, and the alias effect will not occur.
I want to ask a question about the subject. Can we implement such a demodulation with DSPs? Is there a DSP card for this application (TI or Motorola)? I want to learn whether such a demodulation can be implemented on a DSP using simulink automatic code generation tool.
Hi emrek,
u can use DSPs to implement digital demodulators provided the data rate is low.
For higher data rate systems the nof MAC computations will be morem, and u require many multipliers to work simultaneously to sustain the data rate. The difference in the nof Multipliers for the DSPs and FPGAs are high, and so FPGA can give a better performance for the same compared to DSPs
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