punj33
Newbie level 6
IP core I have is in VHDL and my whole program is in Verilog. Since I have just started studying VHDL, its difficult for me to actually get the idea how to instantiate the whole IP.
I have instantiated a simple VHDL entity into Verilog but this IP core is just too complex for me.
The detail of the IP core is:
There are 4 files:1 file includes only package [no entity], 1 file has the main entity which encompasses everything including the entities of other 2 files.
So, the main entity has:
1] included package in their header file work.controller_pkg.all;
2] port mapped the entities within the block statements
So my problem lies in what to instantiate in my verilog module
1] Should I instantiate only the top entity ? Is it that I compile all the files of vhdl separately and instantiate only the top entity
2] Entity has attributes and generics. How do I instantiate them in verilog ?
I have instantiated a simple VHDL entity into Verilog but this IP core is just too complex for me.
The detail of the IP core is:
There are 4 files:1 file includes only package [no entity], 1 file has the main entity which encompasses everything including the entities of other 2 files.
So, the main entity has:
1] included package in their header file work.controller_pkg.all;
2] port mapped the entities within the block statements
So my problem lies in what to instantiate in my verilog module
1] Should I instantiate only the top entity ? Is it that I compile all the files of vhdl separately and instantiate only the top entity
2] Entity has attributes and generics. How do I instantiate them in verilog ?