Differential outputs on Arty-A7

[qamesh]

Hello,
Hi, I am experimenting with differential outputs on the Arty A7. For this, I am using the 100MHz clock and have instantiated an ODDR then OBUFDS -- . I Have also looked through the 7-series Select-IO Resources User Guide and the only differential I/O at 3.3V is TMDS_33 IOStandard.

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Code Verilog - [expand]
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ODDR #(
      .DDR_CLK_EDGE("SAME_EDGE"),
      .INIT(1'b0), 
      .SRTYPE("SYNC")
   )ODDR_CLKADC(
      .Q(buff_local),
      .C(buff_in),
      .CE(1'b1),
      .D1(1'b1),
      .D2(1'b0),
      .R(1'b0),
      .S(1'b0)
   );
 
   OBUFDS  #(
     .IOSTANDARD("TMDS_33") // Specify the input I/O standard
     )OBUFDS_inst (
      .O(buff_out_p),     // Diff_p output (connect directly to top-level port)
      .OB(buff_out_n),   // Diff_n output (connect directly to top-level port)
      .I(buff_local)      // Buffer input
    );

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The .xdc file has the following --

## Pmod Header JB
set_property -dict { PACKAGE_PIN E15 IOSTANDARD TMDS_33 } [get_ports { buff_out_p }];
set_property -dict { PACKAGE_PIN E16 IOSTANDARD TMDS_33 } [get_ports { buff_out_n }];
Pins E15/E16 are HR I/O banks [JB1/2] and they should work fine.

Synthesis & implementation are fine and I can generate a bitstream, but I see no output on these pins (just 0v)
I also tried to connect a termination resistor of 50 ohm pulled up to 3.3 V as recommended for FP_3.3_50 [OFF chip termination]. but it gives nothing...can anyone help me in this?

 

[ads-ee]

What drives buff_in?

You don't show how that is produced, if it never toggles the output of the ODDR will never change. The C input needs both rising and falling edges to output the D1 and D2 inputs.

 

[qamesh]

What drives buff_in?

You don't show how that is produced, if it never toggles the output of the ODDR will never change. The C input needs both rising and falling edges to output the D1 and D2 inputs.

Hello,
buff_in is clk_100MHz (it is. a single ended clock signal of 100 MHZ comes from the Output of the Clock wizard).

#The C input needs both rising and falling edges to output the D1 and D2 inputs.
do you mean that I should set both to 1'b1 ?..I though that it is up to the user to set whether to use the rising edge or the falling edge!.

 

[dpaul]

@qamesh
#The C input needs both rising and falling edges to output the D1 and D2 inputs.
It means the nature of the buff_in signal should be that of a clock (which has periodic rising and falling edges).