Differential inputs & outputs in Verilog

[ikevin]

Hi,
I have a Virtex 5 board and I would like to interface a high-speed DAC and ADC to it.

I have differential 16 bits data and 1 clock in + 1 clock out total. Can I do something like this for differential signals?

	// ADC part
	// check Postive and Negage parts of the clock
	always @ (CLOCK_IN_P or CLOCK_IN_N)
	begin
		CLOCK_IN <= ~CLOCK_IN;
	end
	
	// do the same for DATA1 to DATA15
	always @ (DATA0_P or DATA0_N)
	begin
		if (DATA0_P == 1 && DATA0_N == 0)
			DATA0 <= 1;
		else if (DATA0_P == 0 && DATA0_N == 1)
			DATA0 <= 0;
	end		
	
	// grab the DATA
	always @ (posedge CLOCK_IN)
	begin
		DATA_REG[0]<=DATA0;
		DATA_REG[1]<=DATA1;
		DATA_REG[2]<=DATA2;
		// ... do the same until DATA15
		
		// let the DAC know we're done, lets clock out
		CLOCK_OUT <= ~CLOCK_OUT;
	end
	
	// DAC clock out part
	always @ (posedge CLOCK_OUT)
	begin
		CLOCK_OUT_P <= 1;
		CLOCK_OUT_N <= 0;
	end
	
	always @ (negedge CLOCK_OUT)
	begin
		CLOCK_OUT_P <= 0;
		CLOCK_OUT_N <= 1;
	end

If there is a better way to do it, please let me know. Thanks a lot.

 

[TA37]

Try reading the xilinx ap notes on differential pair. Usually these are considered a single logical signal inside the HDL, you don't see both inputs. Rather the differential nature is a I/O technology specific feature specified in the Xilinx constraint file(s).

What you have shown is problematic and will probably generate a latch for DATA0. The tools have to assume that P=N=0 and P=N=1 are possible. Unless you are explicitly creating black-box *BUFDS* elements in the hdl, see pages 139,140 of https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/virtex5_hdl.pdf.

 

[ikevin]

Thanks for helping TA37. Do you know if I can instantiate the buffers inside the top level module as the following?

module differential_signals_test_top (
input CLOCK_IN_P,
input CLOCK_IN_N,
input [15:0] DATA_IN_P,
input [15:0] DATA_IN_P,
//output CLOCK_OUT_P,
//output CLOCK_OUT_N,
output [15:0] DATA_IN_BUFF
)

reg CLOCK_IN;
reg CLOCK_OUT;
reg [15:0] DATA_IN;
reg [15:0] DATA_IN_BUFF;

IBUFDS #(
.CAPACITANCE("DONT_CARE"),
.DIFF_TERM("FALSE"), 
.IBUF_DELAY_VALUE("0"), 
.IFD_DELAY_VALUE("AUTO"), 
.IOSTANDARD("DEFAULT")
) IBUFDS_inst (
.O(CLOCK_IN), 
.I(CLOCK_IN_P),
.IB(CLOCK_IN_N)
);

OBUFDS #(
.IOSTANDARD("DEFAULT")
) OBUFDS_inst (
.O(CLOCK_OUT_P),
.OB(CLOCK_OUT_N), 
.I(CLOCK_OUT)
);

IBUFDS #(
.CAPACITANCE("DONT_CARE"),
.DIFF_TERM("FALSE"), 
.IBUF_DELAY_VALUE("0"), 
.IFD_DELAY_VALUE("AUTO"), 
.IOSTANDARD("DEFAULT")
) IBUFDS_inst (
.O(DATA_IN), 
.I(DATA_IN_P),
.IB(DATA_IN_N)
);

// send out CLOCK_OUT

// latch DATA_IN to ANOTHER BUFFER AT every CLOCK_IN

always @ (posedge CLOCK_IN)
begin
	DATA_IN_BUFF <= DATA_IN;
end

endmodule

 

[rberek]

Yes, you can.

r.b.